Transistors and other semiconductor devices may be fabricated through a number of subtractive and additive processes. Certain benefits, such as channel mobility for transistors, may be obtained by forming the device layers in semiconductor material other than silicon, such as germanium and III-V materials. Where a crystalline material such as silicon serves as a starting material, epitaxial growth techniques (e.g., hetero-epitaxy) may be utilized to additively form a transistor channel including non-silicon materials on the substrate. Such processes can be challenging for a number of reasons, including but not limited to mismatch between the lattice constants and/or thermal properties of the substrate and the layers epitaxially grown thereon.
Manufacturers of silicon-based field effect transistor (FET) devices have now commercialized devices employing non-planar transistors. Such devices may include a silicon fin that protrudes from a substrate and includes a subfin region (e.g., at least a portion of which is below the surface of a trench dielectric) and an overlying channel. Such devices may also include one or more gate electrodes (hereinafter, “gate” or “gates”) that wrap around two, three, or even all sides of the channel (e.g., dual-gate, tri-gate, nanowire transistors, etc.). On either side of the gate, source and drain regions are formed in the channel or are grown in such a way as to be coupled to the channel. In any case, these non-planar transistor designs often exhibit significantly improved channel control as well as improved electrical performance (e.g., improved short channel effects, reduced short-to-drain resistance, etc.), relative to planar transistors.
Although the devices described above have potential, they may suffer from one or more drawbacks that may limit their usefulness. For example, subfin leakage (leakage between the source and drain of the channel via the subfin region) may hinder the ability of a gate to turn the non-planar transistor OFF. With this in mind, one approach for containing subfin leakage in non-planar devices such as those described above is to dope the subfin region with a dopant of a type (P or N) that is opposite the dopant used in source and drain. Although this approach can be effective, dopant diffusion and Debye lengths can limit the abruptness of the barrier to subfin leakage that is created by this approach.
Design of the conduction band offset (CBO) between the subfin region and the channel of a non-planar semiconductor device is another approach for containing subfin leakage. In that approach, relatively wide CBO and an abrupt heterojunction may be employed to confine channel electrons to the channel region and prevent them from leaking into the subfin region. Manufacturing and existing material considerations, however, can limit the practical usefulness of that approach.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.